Array transformation in a behavioral synthesis tool

ABSTRACT

A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.

FIELD OF THE INVENTION

The present invention relates generally to behavioral synthesis toolsfor creating integrated circuits, and more particularly relates tobehavioral synthesis tools that provide for improved packing of arraysto memory.

BACKGROUND

With the proliferation of data-intensive applications, such as sound,image and video processing, the memory subsystem has become an importantfocus of electronic system design. More than three-quarters of adata-intensive system can be made up of storage components, making thememory subsystem the most crucial part of the design of an integratedcircuit. Most of these systems need to be high-speed due to the largeamounts of data involved and must be designed carefully to avoid asolution that is larger than expected.

The design of an integrated circuit no longer begins with a circuitdiagram. Instead, it begins with a software program that describes thebehavior or functionality of a circuit. This software program is asource code description that defines an algorithm to be performed withlimited implementation details. Designers direct behavioral synthesistools to convert the source code description into a register transferlevel (RTL) description. The RTL description is used to ultimatelygenerate a netlist that includes a list of components in the circuit andthe interconnections between the components. This netlist is used tocreate the physical integrated circuit.

Arrays provide a powerful and convenient method for modeling thebehavior of memories in source code descriptions. That is, behavioraldescriptions are used to manipulate groups of data in an abstract mannerusing arrays. These arrays are, under the control of the designer,packed to memory. Behavioral synthesis tools automatically construct thelogic to control the memory, freeing the designer to explorearchitectures using different memories with different characteristics(e.g., synchronous versus asynchronous, single port versus dual port),and make intelligent decisions about an appropriate implementation for adesign.

To pack arrays to a memory, the designer must specifically assign thevariables representing the arrays to a memory in source code and specifythe type of memory and other memory parameters. This is accomplishedusing a set of attributes or directives. For example, Synopsis® toolsuse a “pragma” statement.

After the designer designates the details of memory allocation in thesource code description (using pragma statements or other directives),the designer runs the source code description through the synthesistool. The synthesis tool generates a report that the designer can use toanalyze the performance of the circuit. For example, the user canexamine the speed and area of the circuit to determine whether thecurrent memory allocation is acceptable. If the memory allocation is notacceptable, the designer must return to an editor, re-edit the sourcecode description to change the details of memory allocation, and run thesource code description through the synthesis tool again. Such atechnique for modifying the memory allocation is time consuming andinefficient and gives the designer only a limited amount of options fordesignating how memory will be allocated.

It is desirable, therefore, to provide a method and synthesis tool thatallows a designer to modify memory resources more quickly and simply aswell as provide the designer with more advanced options for specifyinghow arrays will be packed to memory.

SUMMARY

Methods, systems, and behavioral synthesis tools are provided that allowa designer to change the format of how an array is packed to memoryduring the memory packing process when converting a source codedescription of a circuit to an RTL description. The designer can write asource code description at the algorithmic level describing the behaviorof the circuit to be designed. The designer then uses a behavioralsynthesis tool to generate a number of different architectural designsusing synthesis techniques. Each design can implement differing memoryallocation by allowing the designer to change a number of differentconstraints such as whether to use RAMs vs. registers, which type of RAMto use, how many memories to use, whether to use on or off-chip memory,etc. The designer is also provided the ability to transform the layoutformat of the arrays in the source code description such that thedesigner can quickly and easily control the packing of the arrays intothe chosen memories. These constraints can be changed either using agraphical user interface, changing constraints within the behavioralsynthesis tool, or by manually manipulating the source code description.The behavioral synthesis tool then creates a report for each design toanalyze the performance of the circuit. For example, the designer canexamine and compare the speed and area of the circuits created from eachof the designs to determine whether the memory performance and size areacceptable.

A source code file having a description of the hardware is read into adatabase within the behavioral synthesis tool. The behavioral synthesistool analyzes the source code description and generates a data structureassociated with the source code description. The designer can thenmodify a number of constraints dictating the details of memoryallocation such as type of memory, number of memories, memory size, etc.Thus, rather than having to re-edit the source code description, thedesigner can change these memory constraints interactively anddynamically during the memory packing process to control how arrays arepacked into memory. Once the designer is satisfied with the design, anRTL description is produced from the data structure.

A number of additional options for packing arrays into memory areprovided by the behavioral synthesis tool to the designer so that thedesigner may select one of a plurality of array layout formats duringthe memory packing process. Providing the designer the ability totransform the layout of arrays dynamically allows the designer a fast,efficient method of customizing the memory allocation of the circuit tobe synthesized.

Further features and advantages of the invention will become apparentwith reference to the following detailed description and accompanyingdrawings.

BRIEF DESCRIPTION OF T HE DRAWINGS

FIG. 1 is a block diagram of a system for allowing interactive memoryallocation.

FIG. 2 is a detailed diagram illustrating a design flow for creating anintegrated circuit using the system of FIG. 1.

FIG. 3 is an illustration of directly packing an array to a memory.

FIG. 4( a) is an illustration of packing multiple words of an array intoa single word of a memory.

FIG. 4( b) is another illustration of packing multiple words of an arrayinto a single word of a memory.

FIG. 5( a) is an illustration of packing an array into a memory using aLittle Endian format.

FIG. 5( b) is an illustration of packing an array into a memory using aBig Endian format.

FIG. 6( a) is an illustration of packing an array into memory in aninterlacing format.

FIG. 6( b) is another illustration of packing an array into memory in aninterlacing format.

FIG. 7( a) is an illustration of packing a single word of an array intomultiple words of a memory.

FIG. 7( b) is another illustration of packing a single word of an arrayinto multiple words of memory.

FIG. 8 is an illustration of packing an array into a customized locationin a memory.

FIG. 9( a) is an illustration of packing a single array into multiplememories.

FIG. 9( b) is another illustration of packing a single array intomultiple memories.

FIG. 10 is an illustration of packing multiple arrays into a singlememory.

FIG. 11 is an illustration of packing multiple arrays into a singlememory with the arrays overlapping in memory usage.

FIGS. 12( a-c) are illustrations of using resolution modes to definedefault behavior and correct designer error.

FIG. 13 shows an example of a user interface allowing the designer tomodify memory resources in a behavioral synthesis tool.

FIG. 14 is a block diagram of an embodiment of a network environment forimplementing a behavioral synthesis tool.

FIG. 15 is a block diagram of an embodiment of a system to carry outmethods, systems and tools in accordance with the present invention.

FIG. 16 is an example of applying memory allocation to a SIF.

DETAILED DESCRIPTION

FIG. 1 shows a system 10 for generating an integrated circuit. Adesigner typically creates a behavioral description of an integratedcircuit by generating source code 12 using a separate editor (notshown). The source code description may be written in any programminglanguage capable of describing a circuit at the behavioral level, suchas C, C++, VHDL, Verilog, Pascal, etc. Once the source code description12 is complete, a behavioral synthesis tool 14 reads in the source codedescription 12 and allows a designer to evaluate and modify the circuitarchitecture early in the design process. In particular, the source codedescription 12 is read into an intermediate database 16 that holds thebehavioral description as a data structure. This data structure, calleda synthesis intermediate format (SIF), is modifiable by the user througha graphical user interface (GUI) 18. The GUI 18 allows the designer tointeractively and dynamically modify the memory allocation in the datastructure. However, the designer may also modify the memory allocationby manually editing the original source code description, or modifyingthe SIF without the assistance of a GUI. For instance, the designer mayissue commands to modify the memory allocation within the SIF. Thedesigner may then quickly evaluate the area and latency associated withdifferent memory architectures. Once the designer is satisfied with thearchitecture, the RTL code is generated as shown at 20. Furtherprocessing is then performed on the RTL code to ultimately generate theintegrated circuit.

FIG. 2 shows a more detailed flow chart for generating an integratedcircuit according to one embodiment of the invention. In process block30, the behavioral synthesis tool reads in the source code describingthe behavior of the integrated circuit as already described. The sourcecode description can include a default set of constraints to establishthe original memory allocation. Alternatively, the default constraintscan be provided by a selected packing mode, or by the designer once thesource code description is read into the behavioral synthesis tool. Inprocess block 32, the behavioral synthesis tool 14 (see FIG. 1) readsthe source code description into the intermediate database 16 andgenerates a data structure that is changeable by the designer. Whengenerating the data structure, the synthesis tool performs an analysisof the source code description. For example, the synthesis tool searchesfor operators, signals, and variables in the source code description andgenerates the data structure based on these statements. Additionally,the synthesis tool searches for directives and uses the directives asdefaults for the memory allocation in the data structure.

At this point in the flow, the memory allocation information is storedin the intermediate database independently, meaning the information isnot yet fully integrated into the SIF. This allows the designer tointeractively change the memory allocation and control when such changesare applied to the SIF. The memory allocation information is stored as aset of resources for the design, wherein each resource represents amemory resource that may potentially be present in the final integratedcircuit design. Additionally, arrays in the source code description arealso stored in the data structure. The data structure may be organizedin many different ways. One possible organization is to have variousfields associated with the resources and arrays stored in the datastructure. For instance, in one embodiment the following fields could beassociated with a resource stored in the data structure:

A unique identification for the resource

A type of memory to be used for the resource

A list of variables packed to the resource

A packing mode for the resource

A flag indicating whether the resource is external to the design

A format for packing variables to the resource

Likewise, in one embodiment the following fields could be associatedwith arrays stored in the data structure:

A unique identification for the resource

An array length

An array width

A start address in a resource

A start bit in the resource

A format for packing the array to the resource

In process block 34, the designer can interactively change the memoryallocation for variables that are in the source code description. Thatis, the source code description includes variables representing arraysthat are associated with memory storage (although in some cases arraysare not packed to memory). The memory allocation for variablesrepresenting the arrays is modified by allowing the designer tomanipulate a number of constraints relating to memory allocation. Forinstance, a first constraint may allow the designer to choose from themany different memories available in circuit design. Additionalconstraints may vary the size and type of memory selected (e.g., dualport memory, single port memory, etc.). Thus, in process block 34, thedesigner can choose which memories to use, the variables associated withthose memories, the packing mode, etc.

In order to give the designer more flexibility in design, the designeris also provided the ability in process block 34 to transform the layoutof the arrays into a variety of formats. The format used to pack anarray to memory can have a significant impact on the overall memoryperformance of the circuit. Often the format used will dictate thenumber of reads and/or writes necessary to access a given number ofwords of an array or memory. Various formats can be chosen thatemphasize keeping the size of the circuit within given specifications,while other formats can be chosen that emphasize the speed of thecircuit (reducing the number of clock cycles/reads/writes). Specificarray layout formats will be discussed at length with respect to FIGS.3-11.

The designer can modify any of the memory allocation constraintsdiscussed above (i.e. size, number, and type of memories, packing mode,formats) in a number of ways. The designer can use the GUI 18 shown inFIG. 1 to change constraints controlling memory allocation.Alternatively, the designer could manually change the constraints in theSIF or manually edit the source code description to include theconstraint.

After memory is properly allocated, the designer can perform an initialcheck to analyze the area and timing of the circuit (process block 36).This may be done, for example, by displaying an area versus latencygraph that gives the designer some immediate feedback on whether thememory allocation is satisfactory. If the designer is unhappy with thearea or timing, the designer can return to process block 34 to furthermodify the memory allocation, as shown by arrow 38. On the other hand,if the designer is satisfied with the memory allocation, the RTL codecan be generated and simulated (process blocks 40 and 42). Finally, anRTL synthesis tool can perform RTL synthesis (process block 44) and thegate level design can be verified and analyzed (process block 46).

For each array or memory, there is a fixed data block, which is readfrom or written into it at the same time. This fixed data block iscalled a word. An array or memory can be characterized by the size andnumber of words. The first parameter of a memory or array is the wordsize, which is the number of bits read or written in a single access.The second parameter is the number of words a memory can store. Eachword has a unique address under which it can be read or written, whichis usually a number from 0 to the wordcount-1. Arrays can usually beindexed by an expression which is computed during runtime. Memories ashardware units can have additional parameters such as delays and numberof ports.

Further details are now given on how the memory allocation is applied tothe SIF. After the designer is satisfied with the memory allocation, thedesigner directs the GUI to apply the memory allocation information tothe SIF. Thus, at this point any changes the designer has made to thememory allocation are reflected in the database by modifying theindependent set of resources and their field information. Applying thisinformation to SIF involves several steps:

1. Create a memory data object representing each memory resource. Thisinvolves determining the size of the memory based on the variablespacked to the memory and the size of the variables, along with thepacking mode. Also, since the original variable index may get packed toa different memory address (based on the packing mode and the order ofvariables on the memory), offsets are computed for each array/index.

2. Transform all read/write accesses to any of the variables packed tothe memory resource into corresponding read/write(s) to the createdmemory data object in step 1. Transforming includes modifying the SIFappropriately to reflect the packing of the original array index to theactual memory address location. This packing is dependent on theordering of the variables and the packing mode used. An appropriateoffset is inserted for each array index access. This offset insertion isalso known as address calculation.

Referring to FIG. 16, an example is given of how memory allocation isapplied to the SIF. FIG. 16 shows three segments of code. The first codesegment 160 is sample of basic code for declaring an array A and thenassigning various words of the array to variables. In segment 160, arrayA is declared with an array length of 100 and word width of 32 bits.Subsequently, word 5 of array A is assigned to variable b and word 9 ofarray A is assigned to variable c.

Assume for purposes of this example that the designer has read codesegment 160 into a behavioral synthesis tool and now wishes to transformthe format of this array such that it is only 50 words in width, and 64bits wide. At this point using prior methods, the designer would have tore-edit source code segment 160 to reflect the change, both whendeclaring the array and whenever the array is accessed, as shown in codesegment 162. Code segment 162 shows the declaration of array A changedto reflect the new size, but also the changes that must be made to thesubsequent accesses to the array. In order to ensure the array accesseswill still assign the correct word of array A after the size change, anew address must be calculated for the desired word. Depending on thechanges made, this calculation could be quite difficult. Thus, manuallyproducing this new code requires substantial editing time on the part ofthe designer and is error prone even for the simplest code such as thatshown in FIG. 16. Code written to describe the behavior of integratedcircuits is often much more complex, and therefore the time andpossibility of error rise accordingly.

However, the behavior synthesis tool of the current embodiment allowsthe designer to simply change a constraint to transform the layout ofarray A from 100 by 32 to 50 by 64. Since the source code segment 160has already been read into the SIF, a provided GUI will display thearray A along with its current size, 100 by 32. The designer thenchanges a size constraint for the array indicating the array should betransformed to a 50 by 64 format. Once confirmed, the constraint withinthe SIF for the size of array A is changed to reflect the designer'sdesired change, and the behavioral synthesis tool creates RTL codereflecting any changes in the constraints. In other words, even thoughcode segment 160 was read into the SIF, due to the designer'sconfiguration of the constraints through the GUI, the RTL code iscreated as if the code segment 162 had been originally read in. This canbe accomplished by the behavioral synthesis tool by actually creatingand editing the code segment 160 to reflect the functionality of codesegment 162, editing the SIF of code 160 to reflect the functionality ofcode segment 162, or leave code segment 160 unchanged yet still createRTL code to reflect the functionality of code segment 162.

Alternatively, in another embodiment, the designer could have manuallyadded a size constraint to the source code segment 160, such as thatshown in code segment 164, and then read in code segment 164 to the SIF.In yet another embodiment, the size constraint within the SIF could bechanged manually by the designer without the assistance of a GUI.

Allowing a designer control over how arrays are packed to memory duringthe memory packing process in synthesizing an integrated circuit isdesirable because the chosen architecture will have a significant impacton the performance of the memory system. For example, depending upon howthe array words are accessed, it may be more effective to have the RAMword size different from the array word size. If two consecutive wordsfrom the array are accessed together, it may be efficient to pack twoarray words into a single RAM word. Or, conversely, if half of the arrayword is accessed often, it may be effective to split the array word intotwo RAM words.

Consider two arrays A (word size: 16) and B (word size: 32) are to bepacked together. The RAM word size could be chosen to be, for instance,16 or 32. If a designer chooses 32, the array A words could bezero-padded to make all A and B words the same size. The solution justsuggested is obviously quite wasteful in terms of memory usage. Anothersolution would be to pack two array A words into a single RAM word. Athird solution would be to choose 16 as the RAM word size, and spliteach array B word into two RAM words. A choice between the second andthird formats would be dictated by word access patterns for the twoarrays. Often there are numerous formats available for the same designdescription, each having advantages and disadvantages compared to otherformats.

FIG. 3 is an illustration of directly packing an array to a memory. Inthis example, array 50 and memory 52 are the same length (10 words) andwidth (4 bits). However, array 50 could also be packed to a sub-sectionof a larger memory. In order to pack array 50 to memory 52, word 0 ofarray 50 is packed directly to word 0 of memory 52, as are subsequentwords 1 through 9. Each array access results in one memory access. Thereis no address conversion and array addresses can be used directly asmemory addresses. Therefore, direct packing is fairly simple and isprocessed by the behavioral synthesis tool quickly.

In many cases, access to memory elements is the bottleneck of a design,because it limits the maximum parallelism of the performedfunctionality. One option is to increase the width of a memory word, soeach memory access reads or writes multiple array words. Packing anarray to a memory with larger word size is a typical transformation toincrease the throughput of the memory port as an alternative to memorieswith multiple ports. FIG. 4( a) is an illustration of packing multiplewords of an array into a single word of a memory. Array 60 shown in FIG.4( a) has a length of 10 words and width of 4 bits. Array 60 is packedto a memory 62 that is 8 words in width, or twice the word width ofarray 60. Therefore, words 0 and 1 of array 60 can be packed into word 0of memory 62. Likewise, words 2 and 3 of array 60 are packed to word 1of memory 62, and so on.

FIG. 4( b) is another illustration of packing multiple words of an arrayinto a single word of a memory. Array 64 in FIG. 4( b) has a word widthof 4 bits. However, memory 66 has word width 12, or three times the wordwidth of array 64. Therefore, words 0, 1 and 2 of array 64 can be packedinto word 0 of memory 66. Likewise, words 3, 4 and 5 of array 64 arepacked to word 1 of memory 66, and so on.

Packing multiple array words to a single word of memory requires eacharray access to be transformed into a memory access, where certainaddress calculations and sub-selections of memory words have to beperformed. Writing an element of the array requires reading the memoryword first or the array element sharing the same memory word is notoverwritten. In other words, each array read transforms into a memoryread and an array write transforms into multiple memory accesses. Adesigner would therefore find this format useful if multiple arrayaccesses can be packed to a single memory access. This may be the casewhen the source code description contains numerous loops that access thearray elements in sequential order, or if the source code descriptionalways, or often, accesses the array words in pairs.

FIGS. 5( a) and 5(b) are illustrations of packing an array into a memoryusing Endian formats. Array 70 in FIGS. 5( a) and 5(b) has an arraylength of 10 and word width of 4 bits. Array 70 is packed to a memory 72with a word width of 8 bits, with two array words being packed to asingle memory word, as discussed previously with respect to FIG. 4( a).However, the format, or the word width or length of the array or memory,are not important for purposes of using Endian formats. Endian formats,like all of the formats described herein, can be used in combinationwith other formats to transform array layouts.

FIG. 5( a) is an illustration of packing an array into a memory using a“Little Endian” format. This format packs array 70 to memory 72beginning at the least significant bit of each word of memory 72.Therefore, memory 72 in FIG. 5( a) shows words 0 and 1 of array 70packed to word 0 of memory 72 starting at the least significant bit,words 2 and 3 of array 70 packed to word 1 of memory 72 starting at theleast significant bit, and so on. Little Endian format is used by mostIntel processors for personal computers using a Microsoft Windowsplatform.

FIG. 5( b) is an illustration of packing array 70 into memory 74 using a“Big Endian” format. This format packs array 70 to memory 74 beginningat the most significant bit of each word of memory 74. Therefore, memory74 in FIG. 5( b) shows words 0 and 1 of array 70 packed to word 0 ofmemory 74 starting at the most significant bit, words 2 and 3 of array70 packed to word 1 of memory 74 starting at the most significant bit,and so on. Big Endian format is used by most Motorola processors forpersonal computer using a Macintosh platform.

Interlacing is a format which skips a specified number of words whenreading from an array in order to pack the words to memory in a givenorder. A typical application would be if the odd addressed and evenaddressed words of the array are used in separate parts of thealgorithm. FIG. 6( a) is an illustration of packing an array into memoryin an interlacing format. Array 80 can be packed in an interlacingformat skipping three words for every word packed such that the evenwords of array 80 are packed to the first five words of memory 82 andthe odd words of array 80 packed to the second five words of memory 82.

FIG. 6( b) is another illustration of packing an array into memory in aninterlacing format. In this example, only two words are skipped betweeneach word of array 84 packed to memory 86, and memory 86 is twice theword width of array 84. Therefore, the first two words of array 84 to bepacked to memory 86, words 0 and 3, are packed to the first word of thememory 86. Likewise, words 6 and 9 of array 84 are then packed to thenext word of memory 86, and so on.

FIG. 7( a) is an illustration of packing a single word of an array intomultiple words of a memory. FIG. 7( a) shows array 90 with a width of 8bits being packed to memory 92 with a length of 4 bits. Therefore, thearray words are split so that the first half of array word 0 is packedto the first word of memory 92, and the second half of array word 0 ispacked to word 1 of memory 92. The rest of the array words are split insimilar fashion, such that array word 1 is split and the first half isstored in memory word 2 and the second half in memory word 3, and so on.The array words can be split and packed to the memory words in orderfrom high order bit to low order bit, or vice versa. For instance,memory words 0 and 1 each contain half of array word 0 in memory 92. Thehalves of array word 0 can be packed to memory 92 in any order. Thefirst 4 bits (AB0-AB3) of array word 0 can be packed to memory word 0,or the last four bits (AB4-AB7) of array word 0 can be packed to memoryword 0.

In this case each array access results in multiple memory accesses. Thisdecreases the performance of the design but might be a designconstraint, e.g. when only certain memory word sizes are available.

FIG. 7( b) is another illustration of packing a single word of an arrayinto multiple words of memory. In FIG. 7( b), array 94 with a length of10 words and width of 8 bits is packed onto memory 96 with a width of 6bits. Selecting a memory word size which in not an exact multiple ordevisor of the array word size results in one of the more complicatedaddressing conversions and slicing operations. The first array word,word 0 (8 bits), is packed to memory word 0 (6 bits), and the first 2bits of memory word 1. This leaves 4 bits of unused space in memory word1. Therefore, the first 4 bits of the second array word, word 1, arepacked to the remaining 4 bits of free space in memory word 1, and theremaining 4 bits of array word 1 are packed to memory word 2. Thiscontinues until all array words have been packed to memory 96. In thiscase 14 memory words are required to hold all 80 bits of array 94. Thisleaves 4 unused bits 98 (80 array bits packed to 6*14=84 memory bits),which may be allocated anywhere in memory 96. In FIG. 7( b), these bits98 are allocated at the end of the memory 96.

The packing shown in FIG. 7( b), like FIG. 7( a), requires extensivecalculations to address a certain array element in the memory. However,such a packing could be useful where available memories are veryconstrained. Because array elements are distributed over two memoryelements, multiple memory accesses might be necessary for each arrayaccess.

FIG. 8 is an illustration of packing an array into a customized locationin a memory. Array 100 has a width of 8 bits and length of 4 words.Memory 102 is unspecified in length, but is larger than array 100 andhas an array length of 12. The array 100 can be packed to any locationin memory 102 large enough to be occupied by array 100. In FIG. 8, array100 is packed such that the first word of array 100 is packed to memoryword 6, and is located such that the first bit of array word 0 is packedto bit 4 of memory word 6. Each subsequent word of array 100 is packedto the subsequent word of memory 102, such that the first bit of thearray word is located at bit 4 of the memory word.

FIG. 9( a) is an illustration of packing a single array into multiplememories. Array 110 is 10 words in length and 4 bits in width. There aretwo memories shown, 112 and 114, each of which are 4 bits in width and 5words in length. Array 110 can be packed to the memories in a variety ofways. For instance, array 110 can be packed to the memories 112 and 114by alternately packing each array word to the first memory 112 and thenthe second 114. Such is the case in FIG. 9( a). Word 0 of array 110 ispacked to word 0 of memory 112, and word 1 of array 110 is packed toword 0 of memory 114. Word 2 of array 110 is then packed to word 1 ofmemory 112, and word 3 of array 110 is packed to word 1 of memory 114.This format continues until the remainder of the words in array 110 arepacked to memory.

Alternatively, array 110 could also be packed such that the first 5words of array 110 are packed sequentially into memory 112 and thesecond 5 words of array 110 are packed into memory 114, as shown in FIG.9( b). Splitting an array into two separate memories increases the sizeof the overall circuit, but is effective in increasing the speed of thedesign because the two memories can be accessed independently. Thus, thedesigner has effectively enabled two words of array 110 to be accessedconcurrently.

FIG. 10 is an illustration of packing multiple arrays into a singlememory. Two arrays 120 and 122 are shown with a length of 4 words andwidth of 8 bits. The memory 124 is of an indeterminate width, but largerthan arrays 120 and 122. The length of memory 124 is 12 words. Word 0 ofarray 120 is packed to word 2 of memory 120, with bit 0 of the arrayword being located at bit 4 of word 2 of memory 124. Each subsequentword of array 120 is packed to the subsequent word of memory 120 withthe least significant bit of the array word located at bit 4 of thememory word.

Array 122 is packed so that it occupies space in memory 124 immediatelyadjacent array 120. Thus, word 0 of array 122 is packed to word 2 ofmemory 124, as was word 0 of array 120. However, word 0 of array 122 isdisplaced such that the least significant bit is located at bit 12 ofthe memory word. The subsequent words of array 122 are then packed tothe subsequent words of memory 124, with the least significant bit ofeach array word located at bit 12 of the memory word.

A designer is thus given the alternative selection of increasing thespeed of the circuit by packing one array onto multiple memories asshown in FIG. 9, or reducing the number of memories and therefore, thesize of the circuit, by packing multiple arrays onto the same memory asshown in FIG. 10.

FIG. 11 is an illustration of packing multiple arrays into a singlememory with the arrays overlapping in memory usage. The arrays 130 and132 and memory 134 are the same dimensions as those described withrespect to FIG. 10. However, in this example, arrays 130 and 132 havebeen packed such that the latter portions of word 0 and 1 of array 130overlap in location with the beginning portions of words 2 and 3 ofarray 132. If arrays 130 and 132 have a common lifetime, then theirsections must be disjoint and the packing shown will cause memoryallocation errors. However, if the arrays have dissimilar lifetimes,this configuration may be an effective way of conserving memoryresources.

The formats described with respect to FIGS. 3-11 allow a designerflexibility in adjusting the constraints that dictate an array layoutformat for packing the array into another array or into memory. Forarea-sensitive designs, it is tempting to merge all data into onememory; however this will constrain the memory accesses far more than ifeach array is packed to a separate memory. Greater speed throughconcurrency can be achieved by using multiple memories when available,with the drawback of a greater circuit size.

It is also noteworthy that the described formats can be used either inconjunction with resolution modes. FIG. 12 is an illustration of usingresolution modes to set the default behavior of a design or to correct adesigner error. Assume for the purposes of example that the four arraysshown in FIG. 12( a) were declared in source code read into a SIF, butonly a first resolution mode was specified. Therefore, the positions ofthe arrays in FIG. 12( a) were determined by a set of constraints foreach array according to the first resolution mode. FIG. 12( b) thenshows the positions of the four arrays after the designer subsequentlychanged constraints corresponding to array 144 causing it to overlapwith array 142. The designer can now be given the option of leaving thearrays positioned as shown in FIG. 12( b) (overlapping), changingconstraints to move array 142 or 144 to an alternate position in memoryto correct the problem, or have the array packed elsewhere automaticallybased upon the current resolution mode. Alternatively, the designercould have the array packed elsewhere in memory 140 based on a newlyselected resolution mode. For instance, the designer could choose tocorrect the problem by selecting a second resolution mode as a basis fordetermining a new position for array 144, as shown in FIG. 12( c). Theresolution mode can intelligently handle the task of repositioning thearray 144 in a variety of ways, such as moving the array in anydirection, resizing the array, packing the array to another memoryresource, etc.

FIG. 13 shows an example of a user interface 150 for allowing thedesigner to modify memory resources interactively and dynamically. Theuser interface includes a display pane 152 that lists processes andarray variables accessed within those processes. These processes andarray variables represent the current memory allocation stored in thedatabase 16 and are represented as graphical objects. When the synthesistool 14 generates the data structure stored in database 16, the sourcecode directives regarding variables and memory allocation are identifiedand are used as default settings for memory allocation. Using the GUI, adesigner may choose to create the source code with no directivesindicating memory allocation. In such a case, the designer interactivelyspecifies the memory allocation via the GUI. Alternatively, the designercan include directives in the source code that are used as defaultsettings.

For example, the array 154 selected in GUI 150 is a size 21 by 64,meaning it has words 64 bits in width, and length of 21 words. Thedisplay pane 152 provides a symbolic name of a resource associated withthe variables. In this case, “dct_temp_rsc” is a memory resource usedfor the array 154, named “dct_temp”. The GUI 150 shows a settings tab156 used by the designer to change the memory allocation of the circuitusing the provided constraints. The setting tab 156 in this exampleshows only one of the many constraints that can be provided forcustomizing the memory allocation of a circuit design. Here, the arrayword width constraint can be changed via the input window 158 to adesired width. Once a new width in entered, the display pane 154 willreflect the new width for array dct_temp. At this point the designer maymake other changes such as the format of array dct_temp, other arrays,change the memory type, etc. Or, if he is satisfied, he can then selectthe “OK” button to apply the changes to the SIF.

Any of the aspects of the methods, systems and behavioral synthesistools described above may be performed in a distributed computernetwork. FIG. 14 shows an exemplary network. A server computer 170 mayhave an associated storage device 172 (internal or external to theserver computer). The server computer 170 may be configured to performany of the implementations of the method described above. The servercomputer 170 may be coupled to a network, shown generally at 174. One ormore client computers, such as those shown at 176, 178, may be coupledto the network 174 and interface with the server computer 170 using anetwork protocol.

FIG. 15 shows that a GUI or alternative means for allowing a user toalter memory allocation may be provided on a client. The client theninteracts with a server for providing other aspects of a behavioralsynthesis tool. For instance, in process block 180, the client computertransmits source code describing the behavior of a circuit. The sourcecode could be an original source code or could be an updated version ofpreviously sent source code. In process block 182, the source code isreceived and read into a behavior synthesis tool provided by the server.The source code is then represented in a SIF in process block 184 thatallows memory allocation constraints to be modified by the client. Inprocess block 186, memory allocation information, such as memoryallocation constraints, is transmitted to the client for display to auser. The client can modify the memory allocation information if they sodesire in process block 184, or approve the constraints and leave themunmodified. If the user modifies the constraints, the modifications aretransmitted to the server where process block 190 updates the memoryallocation in the SIF based upon the modifications, and process blocks186 and 188 can be repeated until the user approves the current memoryallocation. When the user does approve the memory allocation, processblock 192 is processed to create RTL code from the SIF containing theapproved memory allocation. Process block 194 then shows the clientreceiving the RTL code from the server.

Having illustrated and described the principles of the illustratedembodiments, it will be apparent to those skilled in the art that theembodiments can be modified in arrangement and detail without departingfrom such principles.

For example, although a particular GUI was shown, the user interface canbe modified to illustrate the variables and resources in a differentway. The particular user interface used is not important to theinvention.

Also, the transformation of arrays from one format to another during thepacking process can be accomplished in a variety of ways. For instance,an array of a first format can be transformed into an intermediate arrayin a second format, and then directly packed into a memory.Alternatively, the array of the first format can be transformed as it isbeing packed into the memory, such that the array is then stored inmemory in the desired second format.

Although the formats and methods described herein are generallyillustrated in isolation for purposes of clarity, one of skill in theart will recognize that the methods and formats for transforming arraylayout described herein may be combined or modified. For instance, anarray being packed into a customized location, such as shown in FIG. 8,may be packed to the customized location in either of the Endian formatsshown in FIG. 5, or packed in an interlacing format as shown in FIGS. 6(a) and 6(b).

Additionally, the data structure stored in database 16 can be structuredin a wide variety of ways. The particular data structure used is notimportant to the invention.

Moreover, although the description focuses on arrays, variables that areassociated with single registers in an integrated circuit may also bemodified using the formats or tools described. Furthermore, any singlevariable or non-array data can be represented as an array and processedby embodiments of the described behavioral synthesis tool.

Although a particular data structure is illustrated, those skilled inthe art recognize that a wide variety of data structures may be used.

In view of the many possible embodiments to which the principles of ourinvention may be applied, it should be recognized that the illustratedembodiment is only a preferred example of the invention and should notbe taken as a limitation on the scope of the invention. Rather, thescope of the invention is defined by the following claims. We thereforeclaim as our invention all that comes within the scope of these claims.

1.-51. (canceled)
 52. A method of interactively allocating memory in abehavioral synthesis tool, comprising: analyzing a source codedescription describing behavior of an integrated circuit, the sourcecode description including one or more array variables; representing thesource code description in an intermediate format, the intermediateformat including memory allocation information for the one or more arrayvariables; and allowing a user to change the memory allocationinformation for at least one of the one or more array variables whilethe source code description is represented in the intermediate formatand before a register-transfer-level (RTL) description of the integratedcircuit is generated using the memory allocation information.
 53. Themethod of claim 52, wherein the method further comprises providing agraphical user interface through which the user can indicate desiredchanges to the memory allocation information.
 54. The method of claim52, further comprising modifying the memory allocation information inthe intermediate format in response to changes input from the user. 55.The method of claim 52, further comprising modifying the source codedescription in response to changes input from the user.
 56. The methodof claim 52, wherein the memory allocation information for one of theone or more array variables includes an array length, and wherein themethod further comprises changing the array length of the one of the oneor more array variables in response to input from the user.
 57. Themethod of claim 52, wherein the memory allocation information for one ofthe one or more array variables includes an array width, and wherein themethod further comprises changing the array width of the one of the oneor more array variables in response to input from the user.
 58. Themethod of claim 52, wherein the memory allocation information for one ofthe one or more array variables includes a memory type, and wherein themethod further comprises changing the memory type for the one of the oneor more array variables in response to input from the user.
 59. Themethod of claim 52, wherein the memory allocation information for one ofthe one or more array variables includes a memory packing format, andwherein the method further comprises changing the memory packing formatfor the one of the one or more array variables in response to input fromthe user.
 60. The method of claim 52, further comprising displaying anarea versus latency graph for at least one of the one or more arrayvariables using current memory allocation information and before the RTLdescription of the integrated circuit is generated using the memoryallocation information.
 61. The method of claim 52, further comprisinggenerating an RTL description of the integrated circuit using the memoryallocation information.
 62. A system, comprising: means for representinga source code description describing behavior of an integrated circuitin an intermediate format, the source code description including one ormore array variables, and the intermediate format including memoryallocation information for the one or more array variables; and meansfor allowing a user to change the memory allocation information for atleast one of the one or more array variables while the source codedescription is represented in the intermediate format and before aregister-transfer-level (RTL) description of the integrated circuit isgenerated using the memory allocation information.
 63. The system ofclaim 62, further comprising means for modifying the memory allocationinformation in the intermediate format in response to changes input fromthe user.
 64. The system of claim 62, further comprising means formodifying the source code description in response to changes input fromthe user.
 65. A synthesis system, comprising: a memory storing anintermediate format representation of a source code description, thesource code description and the intermediate format representationdescribing behavior of an integrated circuit and including one or morearray variables; and a graphical user interface that allows a user tomodify memory allocation information for at least one of the one or morearray variables before a register-transfer-level (RTL) description ofthe integrated circuit is generated using the memory allocationinformation.
 66. The synthesis system of claim 65, wherein the graphicaluser interface displays a list of processes associated with the sourcecode description and array variables accessed with the processes. 67.The synthesis system of claim 65, wherein the graphical user interfaceallows a user to modify an array length of at least one of the one ormore array variables.
 68. The synthesis system of claim 65, wherein thegraphical user interface allows a user to modify a memory type toallocated to at least one of the one or more array variables.
 69. Thesynthesis system of claim 65, wherein the graphical user interfaceallows a user to modify a memory packing format of at least one of theone or more array variables.
 70. The synthesis system of claim 65,further comprising a display configured to display an area versuslatency graph for at least one of the one or more array variables usingcurrent memory allocation information and before the RTL description ofthe integrated circuit is generated using the memory allocationinformation.
 71. The synthesis system of claim 65, further comprising anRTL generator configured to generate an RTL description of theintegrated circuit using the memory allocation information.